A PCB layer stackup is the arrangement of copper and dielectric layers in a printed circuit board. The stackup determines controlled impedance values, EMI radiation levels, and power distribution quality.
Getting the PCB layer stackup right before routing begins prevents the most expensive problems. This guide explains layer roles, proven stackup configurations, and the EMI rules every stackup must satisfy.
The stackup is the foundation of every high-speed PCB design. A well-chosen stackup makes impedance control automatic and EMI suppression structural.
A poor stackup means fighting signal integrity problems at every routing step, with no fix available after fabrication.
What Each Layer in a PCB Layer Stackup Does
Every layer in a PCB layer stackup has a specific electrical role. Click each tab to understand the role and the design rules that apply.
Signal Layer: Where Traces Carry Data
Signal layers carry the PCB traces that connect components. In a high-speed stackup, signal layers must be adjacent to a reference plane to form a controlled-impedance transmission line.
The dielectric thickness between the signal layer and its reference plane determines the trace impedance. Thinner dielectric gives lower impedance for a given trace width. Thicker dielectric gives higher impedance.
Rule: Every high-speed signal layer must have a reference plane directly adjacent to it, with no other signal layer between the trace and its reference plane.
Ground Plane: The Most Important Layer
The ground plane provides the return path for every signal current in the PCB. At high frequencies, the return current flows directly beneath the signal trace in the reference plane.
A solid, unbroken ground plane limits EMI to the small loop between the trace and its reference plane.
A ground plane with slots forces return currents to detour, creating large current loops that radiate EMI.
Rule: Never cut a slot through a ground plane beneath a high-speed signal trace. The ground plane must be solid copper from edge to edge, with only component drill hits as breaks.
Power Plane: A Reference Plane with DC Bias
A power plane carries DC supply voltage across the board. It also acts as a reference plane for signal layers adjacent to it, just like a ground plane.
A power plane and an adjacent ground plane form a distributed capacitor across the full board area. This built-in capacitance supplements decoupling capacitors and supplies transient currents at very high frequencies.
Rule: Keep the power plane and its adjacent ground plane as close together as possible (thin prepreg, typically 75 to 100 micrometres) to maximise the inter-plane capacitance per unit area.
Prepreg and Core: The Dielectric Materials
Prepreg bonds layers together during lamination. Core is a solid dielectric sheet with copper on both sides. Together they determine the dielectric thickness between each pair of adjacent copper layers.
The dielectric constant (Er or Dk) of the prepreg or core material sets the signal propagation speed and, combined with the layer spacing, determines the controlled impedance for every signal layer.
Rule: Always specify the dielectric constant and thickness to your PCB fabricator. Standard FR4 has Er of 4.0 to 4.5 at 1 GHz.
For designs above 5 GHz, low-loss materials like Rogers 4350B improve signal quality.
Interactive PCB Layer Stackup Builder
Select a standard stackup configuration below. The layer diagram updates to show the exact layer arrangement, and the summary explains why each configuration works.
Impedance Control: How the Stackup Sets Trace Impedance
Controlled impedance in a stackup is set by four parameters. Changing any one of them changes the trace impedance.
The stackup must be designed to achieve the correct impedance for every interface on the board simultaneously, using different trace widths on the same signal layer.
5 Stackup Rules That Reduce EMI
EMI in a stackup is determined by current loop area. Every rule below reduces loop area by keeping signals close to their reference planes.
| Rule | What to Do | Why It Reduces EMI |
|---|---|---|
| 1. Keep every signal layer adjacent to a reference plane | No signal layer should be separated from a reference plane by another signal layer. In a 4-layer board, L1 and L4 are signals, L2 and L3 are references. | The return current flows directly beneath the trace in the reference plane. The current loop area equals trace width times dielectric thickness, which is very small. |
| 2. Use thin prepreg between signal and reference layers | Specify 0.08 to 0.15 mm prepreg between each signal layer and its reference plane. This is much thinner than the core material in the middle of the board. | Thinner dielectric tightens the magnetic field coupling between the signal trace and its return current in the reference plane. Tighter coupling means less radiated EMI. |
| 3. Keep power and ground planes adjacent with thin dielectric | Place the power plane and ground plane next to each other with the thinnest available prepreg (0.08 to 0.10 mm). This is the buried capacitance layer pair. | The inter-plane capacitance acts as a distributed decoupling capacitor across the entire board. It suppresses high-frequency power supply noise that individual decoupling capacitors cannot reach. |
| 4. Route high-speed signals as stripline, not microstrip | Embed high-speed signal layers between two reference planes (stripline configuration). Outer signal layers (microstrip) should carry lower-speed signals where possible. | Microstrip radiates EMI from the top surface because there is no reference plane above it. Stripline is enclosed on both sides by reference planes, which act as a Faraday shield and contain the electromagnetic field. |
| 5. Add stitching vias around the board edge | Place ground vias at approximately 3 mm intervals around the full board perimeter, connecting all ground planes together. Also use ground vias adjacent to any via that changes a high-speed signal from one layer to another. | Stitching vias prevent edge currents from circulating around the board perimeter. They also provide a low-inductance return path when a signal changes layers through a via, preventing the return current from being disrupted at the layer transition. |
Good Stackup vs Bad Stackup: What Changes
- Every signal layer is adjacent to a dedicated reference plane
- Thin prepreg (0.10 mm or less) between signal and reference layers
- Power and ground planes adjacent, separated by 0.08 mm prepreg
- High-speed signals routed as stripline (between two references)
- Stitching vias around board perimeter and at every layer-change via
- Ground plane is solid copper with no slots or splits beneath signal traces
- Impedance specified for each signal layer and given to the fabricator in writing
- Two signal layers adjacent with no reference plane between them
- Thick core between signal layer and reference plane (400 to 800 microns)
- Power and ground planes widely spaced (very low inter-plane capacitance)
- High-speed signals routed on outer microstrip layers with no shielding above
- No stitching vias, or stitching vias only at board corners
- Ground plane split across analog and digital sections beneath high-speed traces
- Impedance not specified, fabricator uses default thicknesses
Common PCB Layer Stackup Configurations
| Stackup | Layer Order (top to bottom) | Best For | Limitation |
|---|---|---|---|
| 2-layer | Signal / Signal | Low-frequency analog, DC power, simple logic below 10 MHz | No reference plane. EMI and impedance control are not achievable at high speeds. |
| 4-layer (standard) | Signal / GND / PWR / Signal | Most mixed-signal boards below 200 MHz. USB 2.0, Ethernet, basic FPGA boards. | Only two signal layers. High-density boards may not have enough routing space. |
| 4-layer (alternative) | Signal / GND / GND / Signal | Boards with external power supply, where a dedicated power plane is not needed | No inter-plane capacitance. Requires more discrete decoupling capacitors. |
| 6-layer | Signal / GND / Signal / PWR / GND / Signal | Boards with 3 or 4 high-speed interfaces. Multi-GHz DDR memory, USB 3.0, PCIe Gen 1 to 2. | L3 is a stripline layer, which is harder to access for components and requires extra vias for breakout. |
| 8-layer | Signal / GND / Signal / PWR / GND / Signal / GND / Signal | High-density BGA breakout, multi-GHz SerDes, high-speed memory interfaces, large FPGAs. | Higher cost. Requires careful via stub management to avoid reflections at higher frequencies. |
| 10-layer and above | Multiple signal and reference layers, design specific | Carrier boards, advanced server CPUs, 112 Gbps SerDes, space-constrained high-performance designs | Very high cost. Layer-to-layer registration tolerances become critical. Backdrilling of vias is often required. |
Every PCB fabricator has its own glass weave, resin content, and copper weight tolerances. The same nominal stackup from two different fabricators can produce trace impedances that differ by 5 to 8 ohms. Always provide the impedance targets in the fabrication notes and ask for a controlled impedance test coupon on the panel.
Watch: PCB Stackup Design for Signal Integrity and EMI Explained
PCB Layer Stackup Questions Engineers Ask
Related Articles on This Site
- Essential PCB Design Rules
- PCB Design Fundamentals
- PCB Trace Width Calculator
- How Decoupling Capacitors Work
- What Is Electromagnetic Interference (EMI)?
External References
- PCB Design Guidelines for Reduced EMI | Texas Instruments Application Note SPRAAR7
- PCB Layer Stackup Design Guidelines | Sierra Circuits / ProtoExpress
What We Learn Today
- A PCB layer stackup must keep every signal layer adjacent to a solid reference plane and use thin prepreg to minimise the current loop area between the trace and its return path.
- Controlled impedance is set by four parameters: trace width, dielectric thickness, dielectric constant, and trace thickness. All four are specified in the fabrication notes and must be validated with an impedance test coupon.
- Stripline traces (embedded between two reference planes) have lower EMI than microstrip (outer layer with one reference plane) because the reference planes shield the trace on both sides.